A synchronous digital/analog converter (DAC) may be regarded according to FIG. 1 as a circuit which consists of a converter 1 and a holding component 2. This DAC circuit simultaneously implements the following two operations:                converting a number x(nτ) into an electrical variable, for example voltage v(nτ), current i(nτ) or charge q(nτ). The number x(nτ) is usually represented in a binary code. The quantity τ denotes the sampling period, and n denotes the discrete time.        keeping the electrical variable constant over a time interval which corresponds to the sampling period τ or a fraction thereof. The 0th order holding component 2 is used for this. The electrical variable v(t), i(t) or q(t) is provided in a continuous time form at the output of the holding component 2.        
FIG. 2A shows a synchronous digital signal in the time domain, i.e. the number x(nτ) plotted against time t. The digital signal can be represented as a sequence of Dirac functions. The sampling period τ corresponds to the inverse of the clock frequency fCLK, i.e. 1/fCLK. In the frequency domain (FIG. 3A), the digital signal is formed by an infinite number of repetitions of the signal spectrum around positive and negative multiples of the clock frequency, k·fCLK, k=0, ±1, ±2, . . . . As usual, the frequency band at d.c. (k=0) is referred to as the baseband and the other frequency bands are referred to as sidebands or signal “images”.
In mathematical terms, the conversion of a number into an electrical variable is merely a change of variables, which does not cause any change in the signal spectrum. There are discrete time sample values (x(nτ) and v(nτ), i(nτ), q(nτ)) before and after the conversion.
In contrast to this, the holding operation (holding component 2) transforms the signal from the discrete time domain into the continuous time domain, i.e. it changes the nature of the signal. The signal v(t), i(t) or q(t) exists as a sequence of levels in the time domain (FIG. 2B), whereas it is filtered according to the function sin(πf/fCLK)/(πf/fCLK) in the frequency domain, see FIG. 3B. This function is conventionally referred to as the sinc function. This “free” filtering attenuates mainly the signal images of the signal since, apart from the baseband, they take the value zero at all multiples of the clock frequency fCLK. The attenuation achieved for the signal images is essentially a function of the ratio between the clock frequency fCLK and the bandwidth fB of the signal, i.e. fCLK/fB. Large values of the ratio fCLK/fB cause high attenuation of the signal images which, for a given fixed signal bandwidth fB, necessitates high clock rates. Large values of the ratio fCLK/fB also mean an increase in the flatness of the frequency excursion in the baseband.
Since a digital/analog converter is typically intended to generate the signal without the signal images, a filter 3 is conventionally required so as to attenuate the signal images to a particular required amplitude. The filter is often referred to as an anti-image filter, (AIF) post filter, reconstruction filter, smoothing filter, etc. The filtered signal v*(t), i*(t) or q*(t) at the output of the filter 3 is represented in the time domain (FIG. 20) and in the frequency domain (FIG. 30).
For example, a clock frequency fCLK=13 MHz and a signal bandwidth fB=100 kHz ensures “free” attenuation of 44 dB at the lower edge of the first signal image. At the baseband edge, the flatness of the signal is about 8.45·10−4 dB. With an additional filter 3, it is possible to achieve higher attenuations and flatnesses.
Primarily two approaches have to date been adopted so as to achieve high attenuation of the signal images. The first option is to increase the ratio fCLK/fB and therefore raise the “free” sinc(f) attenuation. In industrial applications, values of the ratio fCLK/fB on the order of several hundred are customary. A disadvantage is the high power use and the great requirement for chip area entailed by an increase in the clock rate. A second option is to use continuous time smoothing filters 3, the order of which is given by a balance between the intended attenuation at the first signal image, the frequency flatness in the baseband and the implementation technology (tuned or untuned). Again, significant costs are incurred with respect to the power consumption, the chip area and the development of such circuits.
At least theoretically, an alternative to the aforementioned options consists in implementing a higher-order holding function at the output of the digital/analog converter. Instead of keeping the electrical variable constant over the clock period τ (keeping the electrical variable constant is referred to as zeroth-order holding), the electrical variable is selected so that it takes information about the preceding values into account when determining the current value (this corresponds precisely to the mode of operation of a filter). It can be shown that higher-order holding components 2 produce higher-order sinck(f) functions with k=2, 3, . . . This concept, however, is very difficult to implement in practice.